One type of prior art flash Erasable and electrically Programmable Read-Only Memory ("flash EPROM") is organized into rows and columns. Memory cells are placed at intersections of word lines and bit lines. The flash EPROM can be programmed by a user. Once programmed, the flash EPROM retains its data until erased by electrical erasure. The erased flash EPROM can then be reprogrammed with new data.
Typically, the prior art flash EPROM includes a control circuit that controls the memory operation of the flash EPROM. The control circuit is typically supplied with control signals (e.g., chip enable CE, output enable OE, and write enable WE) and commands to start the memory operations. The commands typically include read, program, and erase commands. The CE control signal is the power control of the flash EPROM and is used for device selection of the device. The OE control signal is the output control of the flash EPROM. The WE control signal allows writes to the control circuit of the flash EPROM.
One disadvantage of the above-described prior art flash EPROM is that undesirable or unwanted write or programming operations may occur in the flash EPROM during a power-up sequence. This is due to the fact that during system power-up of a system within which the flash EPROM resides, invalid bus conditions may occur. For example, an invalid bus condition occurs when the OE control signal goes active low while the CE and WE control signals are active low. Another example is that when the OE control signal goes inactive high before the CE and WE control signals become inactive high, the invalid bus condition also occurs. The invalid bus condition typically causes the control circuit of the flash EPROM to latch in unwanted or invalid write commands which then cause the control circuit to initiate the undesirable or unwanted write operations. The undesirable or unwanted write operations typically damage data integrity of the data stored in the flash EPROM.
In addition, the invalid bus condition may also occur during normal operation of the flash EPROM. This is typically due to the fact that glitch or noise signals may occur on the bus that causes the WE, CE, and OE signals to become active low together or separately. As described above, the invalid bus condition typically causes unwanted write operations to the flash EPROM.